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Silicon Labs /EFR32MG21B020F1024IM32 /RAC_S /SYMMDCTRL

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Interpret as SYMMDCTRL

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https://regviz.com/r/Silicon Labs/BGM210LA22JNF/RAC_NS/SYMMDCTRL#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (disable)SYMMDENRSDIG 0 (Divideby1)SYMMDDIVRSDIG

SYMMDENRSDIG=disable, SYMMDDIVRSDIG=Divideby1

Fields

SYMMDENRSDIG

SYMMDENRSDIG

0 (disable): undefined

1 (enable): undefined
SYMMDDIVRSDIG

SYMMDDIVRSDIG

0 (Divideby1): undefined

1 (Divideby2): undefined

2 (Divideby4): undefined

3 (Divideby8): undefined

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data